The present invention relates generally to DC:DC power converters, and more specifically to mechanisms for ensuring a non-destructive start at power-up, under no-load or light load conditions, and under overload conditions.
Circuitry to implement DC:DC converters is known in the art. Such circuits receive an input-side DC voltage that is coupled to a input voltage (Vin) via a switching circuit that has a low on impedance and a high off impedance. The result is that Vin is sampled or chopped and transformer-coupled to an output side. On the output side, the transformer-coupled waveform is rectified and filtered to provide a regulated output voltage Vo that may be greater than or less than the input voltage Vin. Feedback from output to input can be used to regulate the sampling duty cycle or frequency to provide an acceptably efficient DC:DC converter in a small form factor.
The present invention may be used with many circuits that electronically sample an input voltage with a switch such that the magnitude of an output voltage can be varied by the parameters of the switch. Such circuits can encompass DC:DC converter topologies including push-pull, and feed forward among others. By way of example, FIG. 1A depicts a so-called voltage-fed push-pull DC:DC converter 10, according to the prior art, as having an input or primary side 20 and an output or secondary side 30. The input and output sides are essentially demarcated by transformer T1, which has input side or primary windings W1, W2, and output side or secondary windings W3-1,W3-2 and W4-1,W4-2. In some applications, windings W1 and W2 are identical, and center tapped windings W3-1,W3-2,W4-1,W4-2 are identical. However, in general the various sets of windings may differ from each other. Because transformer T1 isolate the input side and the side, transformer-coupled topologies such as shown in FIG. 1A are sometimes referred to as isolated DC:DC converters.
The input side 20 of the converter is coupled to a source of DC potential Vin that in some applications may be pre-regulated with a pre-regulator 40 whose output potential is controlled within a known tolerance. In other applications, pre-regulation is omitted and feedback 50 is used to modulate pulse width of drive signals output from a control circuit 60, to regulate the output voltage(s), shown here as V01, V02.
In FIG. 1A, input voltage, which may be the output potential from pre-regulator 30, is sampled or chopped using push-pull switching transistors Q1, Q2 and respective transformer T1 primary windings W1, W2. Control circuit 50 provides complementary drive signals to the input leads of Q1, Q2 such that when Q1 is on, Q2 is off, and vice versa. Although Q1 and Q2 are shown as switching an end of primary windings W1, W2 to ground potential, it is understood that ground potential implies a stable potential. Stated differently, if desired a potential other than 0 V DC might instead be switchably coupled to an end of primary windings W1 and W2. This understanding that ground is simply a convenient reference potential shall apply throughout this disclosure.
On the converter output side 30, center-tapped secondaries W3-1, W3-2, and W4-1, W4-2 of transformer T1 step-up or step-down the chopped waveforms, which are rectified by diodes D1, D2 and inductor L1-capacitor C1, and by diodes D3, D4 and inductor L2-capacitor C2. As described below, in an attempt to reduce voltage stress on the output side rectifier components and to reduce EMI it is customary to insert snubbers, typically a series-coupled resistor-capacitor, across each output winding of T1.
Feedback loop 50 can sample the DC output voltages, here shown as Vo1, Vo2, to control the pulse width (or duty cycle) and/or frequency of the Q1, Q2 drive signals generated by control circuit 60. The secondary windings may output different magnitudes Vo1, Vo2 and the number of windings may be greater or less than two.
It can be difficult to ensure that system 10 (and DC:DC converter topologies other than voltage fed push-pull) operates in a safe mode initially upon start-up or power-on. For example, until output capacitors C1 or C2 become charged, the voltage output Vo1, Vo2 sensed by feedback loop 50 can remain close to zero. Control circuit 60 may falsely interpret this feedback information as commanding more output voltage, e.g., there should be an increase in duty cycle, frequency, and/or amplitude of the drive signals to switches Q1 and Q2.
But until C1 and C2 begin to charge-up, it is normal that the reported output voltage immediately upon start-up will be close to zero. Yet unless feedback loop 50 and/or control circuit 60 can distinguish the start-up under-voltage for Vo1, Vo2 from a steady-state decrease in magnitude of Vo1, Vo2 excessive inrush currents may be caused to flow through Q1 and Q2, perhaps with destructive results.
Various techniques seeking to ensure a safe or soft start-up have been attempted in the art. For example, for a time immediately following power-up, control circuit 60 can impose a pulse-width modulation upon the drive signals to Q1, Q2 to limit the maximum initial current that is allowed to flow through these switches. Control circuit 60 can then increase duty cycle from a guaranteed safe minimum initial start-up duty cycle to a normal operating duty cycle. In some applications, fairly complex circuitry may be required to ensure a safe soft start-up for a DC:DC converter.
Another problem associated with the circuitry of FIG. 1A occurs under no-load or light load condition, e.g., when neither Vo1 nor Vo2 is coupled to a sufficiently low load (not shown). Under such no-load or light-load conditions, an unregulated DC:DC converter can attempt to develop excessive output voltages Vo1, Vo2. Such over-voltage condition is not desirable and can unduly stress various components comprising system 10. Further, when a suitable load is ultimately seen at Vo1, Vo2, the previous high over-voltage condition may contribute to excessive overshoot on the output waveforms, with possible damage to the load(s) and/or system 10.
FIGS. 1B and 1C depict two non-isolating DC:DC converter topologies. In FIG. 1B, switch Q1 is switched on and off digitally by an output signal from control circuit 60. The result produces a chopped or sampled version of Vin at the junction of inductor L and switch Q1. This chopped signal is rectified, e.g., by diode D1 and capacitor C1, to produce a DC output signal Vo1. The Vo1 signal may be fed-back to control circuit 60, which will then alter at least one parameter of the drive signal to Q1 to try to maintain a desired level of Vo1.
Another non-isolated DC:DC converter topology is shown in FIG. 1C. Again, Q1 is switched on and off digitally by an output signal from control circuit 60, and as a result, a sampled fraction of Vin is coupled to inductor L. The resultant sampled or chopped signal is rectified, here by inductor L and capacitor C1. The rectified output voltage Vo1 may be fedback to control circuit 60, which will then attempt to regulate Vo1 by controlling a parameter of the drive signal to switch Q1.
In the configurations shown in FIGS. 1A-1C, switch Q1 (and if present, Q2) may be called upon to conduct excessive current during start-up or power-up to the DC:DC converter circuit. Thus, there is a need for a soft-start mechanism for use with input voltage-sampled circuits, including DC:DC converters of various topologies, both isolating and non-isolating. It should be possible to implement such mechanism reliably without adding undue complexity to the system design. Further, a simple mechanism should be provided to safely limit output voltage developed by such circuits including DC:DC converters under no-load or light-load conditions. Preferably such mechanisms should be compatible such that a DC:DC converter can be provided with both a soft-start start-up mechanism and with no-load/light-load over-voltage protection mechanism.
The present invention provides such mechanisms for use with switching circuits and more particularly with DC:DC converters of essentially any topology.
In a first aspect, the present invention provides a sampled input voltage circuit such as a DC:DC converter with a soft-start mechanism that ensures a safe start-up. The DC:DC converter may have isolating or non-isolating topology, and may be push-pull or non-symmetrical.
In an isolating topology, the DC:DC converter includes at least one switch (Q1, Q2) coupled via a converter transformer (T1) primary winding (W1, W2) to a source of operating input potential (Vin). In a non-isolating topology, the DC:DC converter typically includes a single switch Q1 and an inductor L that is switchingly coupled to a source of operating input potential (Vin).
The present invention recognizes that at least one parameter of the converter output voltage (Vo) may be controlled by varying magnitude of the on-impedance of switch Q1 or switches Q1, Q2 during at least part of the time the switch is on. More specifically, during start-up of DC:DC converters, the on-impedance of Q1, Q2 is intentionally increased to limit a parameter of Vo, e.g., magnitude, until steady-state condition is attained. Once steady-state is reached, the present invention permits the on-impedance of Q1, Q2 to be reduced to a lowest magnitude, which contributes to steady-state operating efficiency of the DC:DC converter. In such mode of operation, the Q1, Q2 drive signals may be referred to as linear mode signals rather than pure digital signals since Q1 and Q2 are permitted to operate in a linear rather than digital mode during start-up and, if necessary, during overload condition.
In one embodiment a time-lag voltage regulator is coupled between the source of input voltage Vin and the driver to the switch device Q1, or devices Q1, Q2. An exemplary time-lag voltage regulator can simply include a series-coupled resistor Rd and capacitor Cd connected between Vin and ground, in which the Rd-Cd node is sampled to provide operating voltage to the driver for the switch devices. At power-on, the Q1, Q2 driver circuit will not receive sufficient operating potential to drive Q1, Q2 in digital mode until a lag time, determined by the Rd-Cd time-constant, passes. After the lag time passes, sufficient voltage is presented to the Q1, Q2 driver circuit to ensure steady-state digital operation (e.g., full-on, full-off) of Q1, Q2.
A second embodiment can also be used with isolating topology DC:DC converters, push-pull or otherwise, or with non-isolating topologies. In this embodiment, the current through switch Q1 or Q1 and Q2 is sampled to obtain a measure of primary drive current and indeed secondary or output drive current. Such current measurement may be made by coupling a sampling resistor Rs0 is in series with the drive device(s) Q1, Q2, for example between the common node or leads of Q1, Q2 and ground (or other reference node).
The primary drive current i0 carried by Q1, Q2 is sampled and compared to a Vref reference voltage, where Vref represents a safe magnitude of i0. The present invention provides an error amplifier whose input potentials are i0xc2x7Rs0 and Vref, and whose output is coupled to the input of a voltage regulator. The voltage regulator output controls the maximum output amplitude or amplitude envelope available from the Q1, Q2 driver, whose outputs are Vg1, Vg2 drive signals. At power-up to the DC:DC converter, the voltage regulator output will have an envelope that begins at substantially zero potential and increases to a maximum envelope potential, perhaps approaching Vin. As a result, the envelope associated with Vg1, Vg2 drive signals will initially be small, but can increase in magnitude. If the voltage given by i0xc2x7Rs greater than Vref, the present invention modulates the input drive signal amplitudes Vg1, Vg2 to Q1, Q2 with an envelope that somewhat linearly approaches full-drive during power-up, to reduce input current. During no-load or light-conditions, Vg1 and Vg2 are amplitude modulated such that Q1 and Q2 intentionally drop potential across their respective Rds impedances. Thus, only a fraction (rather than essentially all) of the Vin potential is dropped across the T1, T2 primaries, which reduces the magnitude of Vo1, Vo2 until no-load or light-load condition ceases.
As long as i0xc2x7Rs greater than Vref, the voltage regulator cause less than full amplitude Vg1, Vg2 drive signals to be output by the Q1, Q2 driver. Thus, rather than couple all of Vin across the T1, T2 primaries (e.g., in an isolating topology), or across inductor L (e.g., in a non-isolating topology), a fraction of Vin is intentionally dropped across the linear Rds drain-source impedance of Q1 or Q2 and resistor Rs0. After power-up, Q1, Q2 are normally operated digitally, e.g., substantially full-on or full-off, with the result that the fraction of Vin dropped across Rds of Q1 or Q2 and Rs0 is negligibly small. Since the sampled current through Rs0 provides a measure of output load current, the present invention can also protect the DC:DC converter against overload condition.
The first and second aspects of the present invention may be used together, or may be used individually.
Other features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail, in conjunction with the accompanying drawings.